The present invention relates to a semiconductor memory device and, in particular, relates to such a memory which has a self diagnosis circuit in a semiconductor chip.
A large capacity semiconductor memory device, for instance, 256 kbit static memory, and 1 Mbit dynamic memory, has recently been developed and reflects the development of a semiconductor producing process. However, due to the complicated structure and the large scale of a memory array in a semiconductor memory device, it has been difficult to manufacture a semiconductor memory device which has no defective cells.
If a complete semiconductor memory device which has no defective cells is required, the yield rate of the semiconductor memory chip decreases considerably, and therefore, the manufacturing cost would increase.
Accordingly, if a defective cell of a semiconductor memory is recovered by circuit means, the yield rate of a large semiconductor memory chip is considerably increased.
Conventionally, a memory chip which has a normal memory array together with a redundant memory cell has been proposed. In that case, when there is a defective cell in a memory array, that defective cell is replaced by a redundant memory cell.
FIG. 1 is a block diagram of a prior static memory device with a redundant cell. In the figure, the reference numeral 1 is a row address driver, 2 is a row address decoder, 3 is a memory array, 4 is a column address driver, 5 is a column address decoder, 6 is a multiplexer, 7 is a data input circuit, 8 is a data output circuit, 9 is a write enable circuit. The memory device of FIG. 1 has a redundant means for the backup of a defective cell, and said redundant means has a spare row address decoder 10, a spare row memory line 11, a spare column address decoder 12, a spare column memory line 13, a spare multiplexer 14, a wiring means P of polysilicon or nichrome wire for coupling a spare row decoder 10 and word lines, and another wire means Q of polysilicon or nichrome for coupling a spare column decoder with bit lines.
When a memory cell coupled with one of word lines (for instance, word line X.sub.2) is defective, a wire means P is selectively cut by a laser beam. Then, when the defective memory cell is selected by the row address driver 1, the defective word line X.sub.2 is switched to the spare row memory line X.sub.s.
Similarly, when a memory cell coupled with the bit line Y.sub.2 of the memory array 3 is defective, the wiring means Q is selectively cut by a laser beam. Then, when the defective cell is selected by the column address driver, that bit line is automatically switched to the spare column memory line Y.sub.s.
Thus, the semiconductor device of FIG. 1 replaces a defective portion to a spare portion, and therefore, the yield rate of a semiconductor chip is substantially improved.
However, the device of FIG. 1 has the disadvantages that the particular laser trimming device for cutting a polysilicon wire, or the particular current source for cutting a nichrome wire is necessary, and that the steps for switching to a spare means is complicated. Further, when a polysilicon wire or a nichrome wire is cut, a surface of a memory chip is polluted by spatters, and therefore, the operational reliability of a memory chip is decreased.